Semiconductor devices and other integrated circuits are susceptible to damage from an electrostatic discharge (ESD) event. For example, an ESD event may occur either during the assembly and packaging of these devices and circuits, or during normal operation of these devices and circuits in an end product. An ESD event occurs when a high potential voltage and current are rapidly discharged into the device or circuit, which typically results in the destruction of devices and circuits that are not protected from ESD events.
FIG. 1 shows a schematic diagram of an ESD protection circuit according to the prior art. ESD protection circuit 100 includes an input/output pad 110, an internal circuit 120, and a multiplicity of diodes 130 and 140 coupled in series to ground. In conventional ESD protection circuits, an ESD event is typically dissipated through a series of diode elements. This can be seen in ESD protection circuit 100, where diodes 130 and 140 are used to dissipate an ESD event, thereby protecting internal circuit 120 from the ESD event.
The use of diodes in the discharge path to dissipate an ESD event is disadvantageous due to the series resistance of each diode. An ESD protection device ideally should have the lowest possible resistance in order to rapidly dissipate an ESD event. As the number of diodes in the discharge path increases, the resistance in the discharge path becomes greater. This affects the ability of the ESD protection device to dissipate an ESD event as rapidly as possible.
Another disadvantage of ESD protection circuit 100 is that it uses large diodes (i.e., diodes that have large widths) in order to effectively dissipate an ESD event. This is particularly true for diodes in compound semiconductor field effect transistor (FET) technology. Among other things, large diodes consume a relatively large amount of area in the component that contains the ESD protection circuit. Consequently, the component must be larger, which, among other things, increases the cost of the component.
FIG. 2 illustrates a plot 200 of the transmission line pulse characteristic 210 of current versus voltage for an ESD protection circuit according to the prior art. The transmission line pulse characteristic 210 reflects the presence of diodes in the discharge path of the ESD protection circuit. A large series resistance in the discharge path can be seen in transmission line pulse characteristic 210 in that the dissipation of current has an increasing effect on voltage.
U.S. Pat. No. 4,930,036 illustrates a prior art ESD protection circuit that attempts to address some of the disadvantages described above. The ESD protection circuit in the '036 patent uses a transistor and a resistor, rather than a multiplicity of diodes, in the discharge path. However, the resistor adds resistance to the discharge path. Consequently, the use of the transistor and resistor, rather than a multiplicity of diodes, is still disadvantageous for the reasons described above. In addition, the ESD protection circuit in the '036 patent requires two power supplies, including a low-level voltage supply and a high-level voltage supply. Among other things, the need for power supplies increases the complexity, and therefore the cost, of the ESD protection circuit, because additional terminals are needed to connect the power supplies to the ESD protection circuit.
U.S. Patent Application Publication No. 2004/0057172 illustrates another prior art ESD protection circuit. The ESD protection circuit in the '172 patent application is implemented using heterojunction bipolar transistor (HBT) technology. One disadvantage of such an ESD protection circuit is that it requires two separate discharge paths, one to dissipate a positive ESD event and another to dissipate a negative ESD event. Among other things, the presence of two discharge paths adds complexity to the ESD protection circuit, consumes space, and increases the cost of the ESD protection circuit. In addition, the ESD protection circuit in the '172 patent application uses at least one diode in series with a transistor in the discharge path. This increases the series resistance in the discharge path, which, as described above, is a disadvantage for ESD protection circuits.